Image display device and display method for image display device
摘要
說明書
The plurality of thin film transistors TFT and pluralities of red subpixels PR, green subpixels PG, and blue subpixels PB are arranged in a matrix form at intersections of the plurality of data signal lines SL and the plurality of gate signal lines GL. The data voltage (data signal) is supplied from source driver 24 to each data signal line SL, and a gate voltage (gate signal) is supplied from gate driver 25 to each gate signal line GL. A common voltage is supplied from a common power source (not illustrated) to the common electrode. When the gate voltage is supplied to gate signal line GL, thin film transistor TFT connected to gate signal line GL is turned on, and the data voltage is supplied to the pixel electrode through data signal line SL connected to thin film transistor TFT.
Pixel row 22 is constructed with the plurality of pixels P arranged in the row direction. Pixel column 23 is constructed with the plurality of pixels P arranged in the column direction. The plurality of pixel rows 22 include a writing line (an example of the first pixel row) and a non-writing line (an example of the second pixel row) (to be described later).
Source driver 24 supplies the data voltage corresponding to the image data to data signal line SL based on the image data and various control signals (for example, a data start pulse signal, a data clock signal, a latch timing signal, and a polarity control signal) acquired from controller 30. The data voltage charges the pixel capacitance. The latch timing signal is a signal for controlling operation timing of source driver 24, and the polarity control signal (POL) is a signal for controlling polarity of the data voltage.
