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Image display device and display method for image display device

專利號
US10867572B2
公開日期
2020-12-15
申請人
Panasonic Liquid Crystal Display Co., Ltd.(JP Hyogo)
發(fā)明人
Tatsuo Itoman; Satoshi Hirotsune
IPC分類
G09G3/36
技術領域
writing,pixel,row,line,in,driver,22a1,crystal,display,data
地域: Himeji

摘要

An image display device includes: a display; gate signal lines including a first pixel row and a second pixel row; a gate driver; data signal lines; a source driver; and a controller that determines whether the second pixel row has correlation with the first pixel row in an image. When determining that the second pixel row has the correlation with the first pixel row, the controller causes the source driver to supply the data voltage corresponding to the first pixel row, causes the gate driver to supply the gate signal to write the data voltage in the first pixel row, and causes the gate driver to supply the gate signal to write the data voltage corresponding to the first pixel row in the second pixel row.

說明書

Source driver 24 operates a shift register (not illustrated) and a sampling latch circuit (not illustrated) of source driver 24 according to the various control signals, and converts the image data into an analog signal using a DA converter circuit (not illustrated), thereby generating the data voltage. Source driver 24 includes an amplifier (not illustrated) that amplifies the positive-polarity data voltage and an amplifier (not illustrated) that amplifies the negative-polarity data voltage, and the data voltage is amplified by the amplifier selected according to the polarity, and supplied to data signal line SL.

Gate driver 25 supplies the gate signal to gate signal line GL based on various timing signals (for example, a gate start pulse signal and a gate clock signal) acquired from controller 30. Gate driver 25 generates the gate signal by operating a shift register (not illustrated) of gate driver 25 according to the gate clock signal and the gate start pulse signal. That is, gate driver 25 starts output of the gate signal to gate signal line GL in synchronization with the gate start pulse signal. Gate driver 25 sequentially supplies the gate signal to one side in the column direction (for example, from a top to a bottom) of the plurality of pixel rows 22. Gate driver 25 switches gate signal line GL that outputs the gate signal each time the gate clock signal is input.

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