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Data storage device employing staggered servo wedges to increase capacity

專(zhuān)利號(hào)
US10867629B1
公開(kāi)日期
2020-12-15
申請(qǐng)人
Western Digital Technologies, Inc.(US CA San Jose)
發(fā)明人
Toshihisa Kiyonaga; Satoshi Yamamoto; Peng Huang
IPC分類(lèi)
G11B5/55
技術(shù)領(lǐng)域
servo,sectors,disk,pes,vcm,24n,in,phase,22n,offset
地域: CA CA San Jose

摘要

A data storage device is disclosed comprising a voice coil motor (VCM) having a resonance frequency, a first disk surface comprising a first set of servo sectors written at a frequency less than twice the VCM resonance frequency, and a second disk surface comprising a second set of servo sectors circumferentially offset from the first set of servo sectors and written at a frequency less than twice the VCM resonance frequency. An access of the first disk surface is performed by reading at least one of the first set of servo sectors to generate a first position error signal (PES), reading at least one of the second set of servo sectors to generate a second PES, and controlling the VCM based on the first PES and the second PES to position a first head over the first disk surface while accessing the first disk surface.

說(shuō)明書(shū)

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Any suitable control circuitry may be employed to implement the flow diagrams in the above embodiments, such as any suitable integrated circuit or circuits. For example, the control circuitry may be implemented within a read channel integrated circuit, or in a component separate from the read channel, such as a data storage controller, or certain operations described above may be performed by a read channel and others by a data storage controller. In one embodiment, the read channel and data storage controller are implemented as separate integrated circuits, and in an alternative embodiment they are fabricated into a single integrated circuit or system on a chip (SOC). In addition, the control circuitry may include a suitable power large scale integrated (PLSI) circuit implemented as a separate integrated circuit, integrated into the read channel or data storage controller circuit, or integrated into a SOC.

In one embodiment, the control circuitry comprises a microprocessor executing instructions, the instructions being operable to cause the microprocessor to perform the flow diagrams described herein. The instructions may be stored in any computer-readable medium. In one embodiment, they may be stored on a non-volatile semiconductor memory external to the microprocessor, or integrated with the microprocessor in a SOC. In another embodiment, the instructions are stored on the disk and read into a volatile semiconductor memory when the disk drive is powered on. In yet another embodiment, the control circuitry comprises suitable logic circuitry, such as state machine circuitry. In some embodiments, at least some of the flow diagram blocks may be implemented using analog circuitry (e.g., analog comparators, timers, etc.), and in other embodiments at least some of the blocks may be implemented using digital circuitry or a combination of analog/digital circuitry.

權(quán)利要求

1
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