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Data buffer and memory device having the same

專利號
US10867640B2
公開日期
2020-12-15
申請人
SK hynix Inc.(KR Gyeonggi-do)
發(fā)明人
Jin Ha Hwang
IPC分類
G11C16/26; G11C7/10; G11C7/06
技術(shù)領(lǐng)域
en_1,en_2,memory,node,data,may,voltage,transistor,pmos,d_out
地域: Gyeonggi-do

摘要

There are provided a data buffer and a memory system having the same. The data buffer includes first and second amplifiers configured to output output data by inverting input data, the first and second amplifiers having coupled output nodes to which the output data is output, wherein both of the first and second amplifiers are activated to output the output data when the input data has a first swing level, and wherein one of the first and second amplifiers is activated to output the output data when the input data has a second swing level narrower than the first swing level.

說明書

According to an aspect of the present disclosure, there is provided to a data buffer including first and second amplifiers configured to output output data by inverting input data, the first and second amplifiers having coupled output nodes to which the output data is output, wherein both of the first and second amplifiers are activated to output the output data when the input data has a first swing level, and wherein one of the first and second amplifiers is activated to output the output data when the input data has a second swing level narrower than the first swing level.

According to another aspect of the present disclosure, there is provided a data buffer including: a first amplifier configured to output data obtained by inverting input data in a first mode, the first amplifier configured to output data that is of a low level to an output node based on the input data in a second mode in which a swing level of data is different from that of data in the first mode; and a second amplifier configured to output data obtained by inverting the input data together with the first amplifier in the first mode, the second amplifier configured to output data that is of a high level to the output node based on the input data in the second mode.

According to still another aspect of the present disclosure, there is provided a memory device including: a memory cell array configured to store data; a peripheral circuit configured to perform various operations of the memory cell array; and control logic configured to control the peripheral circuit, based on a command, an address, and input data, which are received through a channel, wherein the peripheral circuit includes a data buffer configured to transfer, within the peripheral circuit, data generated in different modes according to swing levels of the input data received through the channel.

權(quán)利要求

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