The column decoder 240 may transfer data between the input/output circuit 250 and the page buffer group 230 in response to a column address CADD. For example, the column decoder 240 may exchange data with the page buffers PB1 to PBI through data lines DL, or exchange data with the input/output circuit 250 through column lines CL.

The input/output circuit 250 may transfer a command CMD and an address ADD, which are received from an external device, for example, the memory controller 2120 of FIG. 6, to the control logic 300, or exchange data DATA with the column decoder 240. For example, when a debugging command, an address, and debugging information are received from the memory controller 2120, the input/output circuit 250 may transmit the debugging command and the address to the control logic 300, and transmit the debugging information to the column decoder 240. The above-described data buffer 1000 of FIGS. 1 to 5 may be included in the input/output circuit 250.

In a read operation or a verify operation, the current sensing circuit 260 may generate a reference current in response to a permission bit VRY_BIT<#>, and output a pass signal PASS or a fail signal FAIL by comparing a sensing voltage VPB received from the page buffer group 230 with a reference voltage generated by the reference current.