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Data buffer and memory device having the same

專利號
US10867640B2
公開日期
2020-12-15
申請人
SK hynix Inc.(KR Gyeonggi-do)
發(fā)明人
Jin Ha Hwang
IPC分類
G11C16/26; G11C7/10; G11C7/06
技術(shù)領(lǐng)域
en_1,en_2,memory,node,data,may,voltage,transistor,pmos,d_out
地域: Gyeonggi-do

摘要

There are provided a data buffer and a memory system having the same. The data buffer includes first and second amplifiers configured to output output data by inverting input data, the first and second amplifiers having coupled output nodes to which the output data is output, wherein both of the first and second amplifiers are activated to output the output data when the input data has a first swing level, and wherein one of the first and second amplifiers is activated to output the output data when the input data has a second swing level narrower than the first swing level.

說明書

Referring to FIG. 11, the memory system 30000 may be implemented as a cellular phone, a smart phone, a tablet PC, a personal digital assistant (PDA), or a wireless communication device.

The memory system 30000 may include the memory device 2110 and the memory controller 2120 capable of controlling an operation of the memory device 2110. The memory controller 2120 may control a data access operation of the memory device 2110, e.g., a program operation, an erase operation, a read operation, or the like under the control of a host 2200.

Data programmed in the memory device 2110 may be output through a display 3200 under the control of the memory controller 2120.

權(quán)利要求

1
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