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Data buffer and memory device having the same

專利號
US10867640B2
公開日期
2020-12-15
申請人
SK hynix Inc.(KR Gyeonggi-do)
發(fā)明人
Jin Ha Hwang
IPC分類
G11C16/26; G11C7/10; G11C7/06
技術領域
en_1,en_2,memory,node,data,may,voltage,transistor,pmos,d_out
地域: Gyeonggi-do

摘要

There are provided a data buffer and a memory system having the same. The data buffer includes first and second amplifiers configured to output output data by inverting input data, the first and second amplifiers having coupled output nodes to which the output data is output, wherein both of the first and second amplifiers are activated to output the output data when the input data has a first swing level, and wherein one of the first and second amplifiers is activated to output the output data when the input data has a second swing level narrower than the first swing level.

說明書

A radio transceiver 3300 may transmit and receive radio signals through an antenna ANT. For example, the radio transceiver 3300 may convert a radio signal received through the antenna ANT into a signal that can be processed by the host 2200. Therefore, the host 2200 may process a signal output from the radio transceiver 3300 and transmit the processed signal to the memory controller 2120 or the display 3200. The memory controller 2120 may transmit the signal processed by the host 2200 to the memory device 2110. Also, the radio transceiver 3300 may convert a signal output from the host 2200 into a radio signal, and output the converted radio signal to an external device through the antenna ANT. An input device 3400 is capable of inputting a control signal for controlling an operation of the host 2200 or data to be processed by the host 2200, and may be implemented as a pointing device such as a touch pad or a computer mount, a keypad, or a keyboard. The host 2200 may control an operation of the display 3200 such that data output from the memory controller 2120, data output from the radio transceiver 3300, or data output from the input device 3400 may be output through the display 3200.

FIG. 12 is a diagram illustrating a memory system according to another embodiment of the present disclosure, for example, the memory system including the memory device 2110 and the memory controller 2120 shown in FIG. 6.

權利要求

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