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Data buffer and memory device having the same

專利號(hào)
US10867640B2
公開(kāi)日期
2020-12-15
申請(qǐng)人
SK hynix Inc.(KR Gyeonggi-do)
發(fā)明人
Jin Ha Hwang
IPC分類
G11C16/26; G11C7/10; G11C7/06
技術(shù)領(lǐng)域
en_1,en_2,memory,node,data,may,voltage,transistor,pmos,d_out
地域: Gyeonggi-do

摘要

There are provided a data buffer and a memory system having the same. The data buffer includes first and second amplifiers configured to output output data by inverting input data, the first and second amplifiers having coupled output nodes to which the output data is output, wherein both of the first and second amplifiers are activated to output the output data when the input data has a first swing level, and wherein one of the first and second amplifiers is activated to output the output data when the input data has a second swing level narrower than the first swing level.

說(shuō)明書(shū)

The mode switching circuit 1200 may output the first enable signal EN_1 or the second enable signal EN_2 depending on a mode of an electronic device (e.g., a memory device) including the data buffer 1000. The mode switching circuit 1200 typically does not simultaneously activate and output the first and second enable signals EN_1 and EN_2. The first and second enable signals EN_1 and EN_2 may be output depending on a swing level of the input data DATA_IN. The data transmission circuit 110 may operate in a particular mode depending on the first or second enable signal EN_1 or EN_2.

When the input data DATA_IN has a first swing level, the mode switching circuit 1200 may output the first enable signal EN_1. At this time, the second enable signal EN_2 may be inactivated.

FIG. 2 is a diagram illustrating data modes in which swing levels of data are different from each other according to an embodiment of the present disclosure.

權(quán)利要求

1
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