白丝美女被狂躁免费视频网站,500av导航大全精品,yw.193.cnc爆乳尤物未满,97se亚洲综合色区,аⅴ天堂中文在线网官网

Data buffer and memory device having the same

專利號
US10867640B2
公開日期
2020-12-15
申請人
SK hynix Inc.(KR Gyeonggi-do)
發(fā)明人
Jin Ha Hwang
IPC分類
G11C16/26; G11C7/10; G11C7/06
技術(shù)領(lǐng)域
en_1,en_2,memory,node,data,may,voltage,transistor,pmos,d_out
地域: Gyeonggi-do

摘要

There are provided a data buffer and a memory system having the same. The data buffer includes first and second amplifiers configured to output output data by inverting input data, the first and second amplifiers having coupled output nodes to which the output data is output, wherein both of the first and second amplifiers are activated to output the output data when the input data has a first swing level, and wherein one of the first and second amplifiers is activated to output the output data when the input data has a second swing level narrower than the first swing level.

說明書

The voltage selection circuit 1110 may be supplied with the first and second voltages Vp1 and Vp2, and be coupled to the ground voltage terminal. The voltage selection circuit 1110 may be implemented with a multiplexer using the first voltage Vp1, the ground voltage VSS and the second voltage Vp2 in response to the first or second enable signal EN_1 or EN_2. For example, the voltage selection circuit 1110 may output the second voltage Vp2 as first and second internal voltages INBP and INBN in response to the first enable signal EN_1. The voltage selection circuit 1110 may output and use the first voltage Vp1 and the ground voltage VSS respectively as the first internal voltage INBP and the second internal voltage INBN in response to the second enable signal EN_2. The voltage selection circuit 1110 may include a first switch SC1 for transferring the first voltage Vp1 to a first node D1 in response to the second enable signal EN_2 and a second switch SC2 for transferring the second voltage Vp2 to the first node D1 in response to the first enable signal EN_1. Also, the voltage selection circuit 1110 may include a third switch SC3 for transferring the ground voltage VSS to a second node D2 in response to the second enable signal EN_2 and a fourth switch SC4 for transferring the second voltage Vp2 to the second node D2 in response to the first enable signal EN_1.

The first amplifier 1120 and the second amplifier 1130 may commonly receive the input data DATA_IN, and output the output data DATA_OUT in response to the first or second enable signal EN_1 or EN_2.

權(quán)利要求

1
微信群二維碼
意見反饋