FIGS. 5A and 5B are flow diagrams depicting an processes for controlling a ready signal of a memory. FIGS. 5A and 5B are described with reference to FIG. 1 for context, but the methods are applicable to other structures as well. In the example of FIG. 5A, at 502 a master device issues a read command to the memory received at 110. At 504, a determination is made by pattern detection circuitry 104 as to whether the current read operation will be a fast operation (e.g., the word that is to be read from is already present in the multiplexer). If so, then the ready signal is asserted at 506 (e.g., by pulling up the shready signal at 120), the SRAM read circuitry 102 outputs data, and a next read command can be received at 110, as indicated back at 502. If not, the ready signal is deasserted at 508 (e.g., by pulling down the shready signal at 120) for one or more clock cycles, as indicated at 510.