FIG. 9 is a diagram depicting performance of a memory that includes pattern matching circuitry under a worst case scenario. In the example of FIG. 9, when a third write command is received along with its associated data (D2) and address (A2) from the master device 902, the pattern matching circuitry detects that the third write command is not writing to the same data word as the first write command on the first write path. Thus, the next write command will not be performed in the best case scenario time, instead taking close to 0.99 ns to complete. The pattern detecting circuitry of the memory 904 deasserts the RDY signal for the fourth clock cycle, indicating to the master device 902 to hold the fourth write command for an additional clock cycle. As indicated in FIG. 9, as an alternative to using the RDY signal to inform the master device 902 that the master device 902 should wait, the master device 902 can determine, based on its sending consecutive write commands that reference bytes in different data words, that the master device 902 should wait a predetermined one or more clock cycles on its own, before sending (or deasserting) a next write command.