As a further example, a system includes a master device operating at a first clock rate. A random access memory is configured to receive commands from the master device, where the random access memory is capable of responding to data read commands matching a pattern at a first rate that is at least as fast as the first clock rate, and where the random access memory cannot respond to data read commands that do not match the pattern as fast as the first clock rate. The random access memory comprises pattern matching circuitry configured to determine whether received read commands match the pattern based on at least a current read command and an immediate prior read command, where the random access memory outputs a ready signal indicating to the master device that the random access memory can receive read commands at the first clock rate when the pattern matching circuitry determines a match.

The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.