FIG. 1 is a diagram depicting a random access memory read path that includes pattern detection circuitry. The random access memory 100 (e.g., a static random access memory (SRAM)) includes read circuitry 102 and pattern matching circuitry 104 for identifying when read commands can be performed faster than a worst case time period. The read circuitry 102 includes a row decoder 106 and a column decoder 108 used to select a row and column of data to be read from the memory 100 based on an address inputted to the pattern detection circuitry 104 at 110. In the example of FIG. 1, a 12 bit address is provided to the memory 100 at point 110 to select a byte of memory to be read from the memory and outputted at 112. The 8 high order bits of that address are provided to the row decoder to select a row containing a word of interest from the storage cells 114 of the memory 100. The 4 low order bits are provided to the column detector 108 to select a byte from a selected row for output at 112 via multiplexer 116.