In certain implementations, read commands appearing as an address at the row and column decoders 108 can take different amounts of time to complete depending on the circumstances. For example, certain lag is introduced into a series of consecutive read operations when the byte being read in a current read operation is different than the byte read in a previous read operation. This lag results from the need for the column decoder 106 to decode the high order address bits indicating the row/word where the desired byte of data is located, select the row of memory in the memory cells 114, and copy that word of data to the multiplexer 116 input. This lag is not present in instances where read operations consecutively read from the same row/data word. There, the selected data word remains in the multiplexer 116, and the desired byte is selected via the bottom order address bits inputted to the column decoder 108 to generate a selection signal to the multiplexer 116. In one experiment, the best case data read access time, when data is read consecutively from a common word, was 0.34 ns, while the worst case data read time where data in consecutive reads is from different data words is 0.94 s.

Typical systems operate according to the worst case operation time. Thus, for a memory having a worst case read time of 0.94 ns, a specification for that memory would traditionally state that read operations cannot be performed faster than that worst case time (e.g., a specification would state that read operations cannot be received faster than one per 1.0 ns). The pattern detection circuitry 104 of FIG. 1 enables the memory to output a signal (shready) indicating to entities within or external to the memory 100 that the memory 100 is ready to receive a next command faster than the worst case timing.