In the example of FIG. 1, the pattern detection circuitry 104 includes a latch 118 and a comparator 120. The comparator 120 is configured to compare the high order address bits received with read commands at 110 to determine if a word being accessed in a current read operation is the same word that was accessed in a prior read operation. The comparator receives the 8 high order address bits for the current read operation from 110 and the 8 high order bits from the immediately prior read operations from the latch at 118. If those high order bits match, then the read operations are accessing the same word in the memory cells 114, and the current read operation will occur faster than the worst case timing. The comparator 120 asserts the shready signal, actively indicating (e.g., to an external master circuit) that a next read operation can be sent quickly, because the current read operation will be completed faster than the worst case time. The current read address is provided to the latch 118 for use in a next pattern detection operation. As an alternative to use of the shready signal, upon sending read commands that request data from two different data words, an external master circuit could, on its own, wait a predetermined number of one or more clock cycles before sending a next read command.