FIG. 2 is a timing diagram indicating one mechanism for handling transmission of read commands to a memory that completes read operations in differing (e.g., between a best case and a worst case time) times. In the example of FIG. 2, a 1 ns clock that is slower than the worst case timing is used. Read commands are consistently sent from a master device 202 to the SRAM 204 1 ns apart, and read data is returned in 1 ns increments. The mechanism of FIG. 2 results in sixteen read operations being performed in 17 ns regardless of whether the data being read is from one or sixteen different data words.

FIG. 3 is an example of a second mechanism for transmitting read commands that takes advantage of pattern detection circuitry in a memory. In the example of FIG. 3, a clock having a period of 0.5 ns is used. This clock is faster than the time necessary to perform a worst case read of 0.94 ns. Read commands cannot, thus, be blindly sent by the master device 302 at a 0.5 ns rate, as worst case reads would not complete before a next read command was received by the SRAM 304, causing a conflict or crash. The SRAM, thus, uses a ready signal (RDY) to indicate when read operations will be performed quickly (e.g., at the 0.34 ns rate) and that the master device 302 should send a next read operation promptly during the next 0.5 ns clock cycle.