In the example of FIG. 3, a first read request (R) and corresponding address (A0) is sent during the first 0.5 ns clock cycle. Because the high order address bits for that read indicate a data word that has not already been loaded (e.g., into the multiplexer 116 of FIG. 1), the pattern matching circuitry does not indicate a match, and the RDY signal is pulled low for one clock cycle, allowing the SRAM to perform the worst case (0.94 ns) read operation. Accordingly, the master device 302 asserts a next read request and corresponding address (A1) over a two clock cycle (i.e., 1.0 ns) time period. In the example of FIG. 3, that second read request requests a byte (or multiple bytes) of data from the same word as the first read request. The pattern matching circuitry detects a match between the high order bits of the first read request address (A0) and the second read request address (A1) and outputs a high RDY signal indicating that the current read request will be performed quickly. The high RDY signal informs the master device 302 that a third read request and corresponding address (A2) can be sent a mere one clock cycle (0.5 ns) later. When that third read request's address (A3) has common high order address bits as the second request's address, the pattern matching circuitry continues to assert the RDY signal high indicating a fast read operation, and the fourth read request can be sent immediately during the next 0.5 ns clock cycle. As indicated in FIG. 3 and described above, as an alternative to use of the RDY signal, upon sending consecutive read commands that request data from two different data words, the master 302 could, on its own, wait a predetermined number of one or more clock cycles before sending a next read command.