Thus, the example timing of FIG. 3, enabled by the pattern matching circuitry and the corresponding signaling of the RDY signal enables sixteen consecutive read operations from the same row or data word to be performed in 9 ns, compared to 17 ns in the example of FIG. 2.

FIG. 4 is a diagram depicting performance of a memory that includes pattern matching circuitry under a worst case scenario. In the example of FIG. 4, each read request asks for data from a different data word, requiring loading of a new data word(s) into the multiplexer. Thus, each time the pattern matching circuitry compares the high order address bits from a current read operation to the high order address bits from an immediate prior read operation, no match is found and the pattern matching circuitry pulls the RDY signal low for one 0.5 ns clock cycle. (In one embodiment, the master device asserting the same address (e.g., A1) for two clock cycles results in the comparator (e.g., an AND-gate) of the pattern matching circuitry pulling the RDY signal high for the second clock cycle indicating to the master device 402 that a next command can be sent.) Even in a worst case scenario, as depicted in FIG. 4, sixteen read operations can be performed in 16.5 ns—better than the 17 ns necessary in the example of FIG. 2. Again as indicated in FIG. 4, as an alternative to use of the RDY signal, upon sending consecutive read commands that request data from two different data words, the master 402 could, on its own, wait a predetermined number of one or more clock cycles before sending a next read command.