The stability of the magnetizations for the AP1 and AP2 pinned layers is very important for optimum p-MTJ performance in that the antiparallel alignment of the two layers provides the proper spin current for magnetization switching of the free layer during a write process. Ideally, a single domain is formed in both of the AP1 and AP2 layers. However, as a result of the MRAM fabrication process, multiple domains generally form in both pinned layers. Accordingly, spin current during a write process is often weak and insufficient to switch the free layer magnetization.

In order for p-MTJs to be more competitive with competing memory technologies, write performance must be significantly improved while maintaining the other critical device properties such as DRR. Since STT-MRAM is typically embedded in Complementary Metal Oxide Semiconductor (CMOS) devices, the pinned layer and free layer magnetizations must withstand thermal processing up to 400° C. temperatures.

One objective of the present disclosure is to provide an initialization process to eliminate multiple domains in a pinned layer in a p-MTJ cell such that the current needed to switch free layer magnetization is more uniform and minimized across a plurality of p-MTJ cells in memory devices including MRAM and STT-MRAM, and in other spintronic devices.

A second objective of the present disclosure is to perform the initialization process according to the first objective such that the error rate for switching free layer magnetization is less than 10 ppm.