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Read circuit for magnetic tunnel junction (MTJ) memory

專利號
US10867652B2
公開日期
2020-12-15
申請人
Taiwan Semiconductor Manufacturing Co., Ltd.(TW Hsinchu)
發(fā)明人
Gaurav Gupta; Zhiqiang Wu
IPC分類
G11C11/00; G11C11/16; H01L27/22; H01L43/02; H01L43/10
技術(shù)領(lǐng)域
mtj,nlr,rnlr,memory,read,layer,imtj,current,cell,tmr
地域: Hsin-Chu

摘要

In some embodiments, the present application provides a memory device. The memory device includes a first current mirror transistor, a first pull-up read-enable transistor, an MTJ memory cell, a first pull-down read-enable transistor, and a first non-linear resistance device. The MTJ memory cell includes an MTJ memory element and a first access transistor. The first non-linear resistance device is coupled in series and between the first pull-up read-enable transistor and the first current mirror transistor. The first non-linear resistance device is configured to provide a first resistance when conducting a first current and a second resistance greater than the first resistance when conducting a second current smaller than the first current.

說明書

A synthetic anti-ferromagnetic (SyAF) layer 105 is disposed under the reference layer 106 or at one side of the reference layer 106 opposite to the free layer 108. The SyAF layer 105 is made of ferromagnetic materials having constrained or “fixed” magnetization directions. This “fixed” magnetization direction can be achieved in some cases by an initializing exposure to a high magnetic field after the entire chip is manufactured. As an example, the SyAF layer 105 may comprise a pair of pinning layers including a first pinning layer 114 and a second pinning layer 118. The first pinning layer 114 and the second pinning layer 118 may have opposite magnetization directions aligned with the magnetization direction of the reference layer 106. Using the same example given above, the first pinning layer has the same “up” magnetization direction with the reference layer. The second pinning layer has an opposite “down” magnetization direction aligned and is anti-paralleled with the magnetization direction of the reference layer 106. An interlayer spacer layer 116 is disposed between the first pinning layer 114 and the second pinning layer 118. The interlayer spacer layer 116 can be an anti-parallel coupling (APC) layer that causes an interexchange coupling (IEC) between the first pinning layer 114 and the second pinning layer 118 such that the first pinning layer 114 and the second pinning layer 118 have anti-parallel magnetic directions and stable each other. As an example, the interlayer spacer layer 116 may comprise ruthenium (Ru) or Iridium (Ir). The first pinning layer 114 may include cobalt layers and nickel layers one stacked above another (Co/Ni)m. The first pinning layer 114 may also be cobalt palladium stack (Co/Pd)m, or cobalt platinum stack (Co/Pt)m, where m can be a positive integer. The second pinning layer 118 may comprise a reverse of the compositions of the first pinning layer 114 with the same or different amount of layers. For example, the second pinning layer 118 may include nickel layers and cobalt layers one stacked above another (Ni/Co)n, or palladium cobalt stack ((Pd/Co)n, or platinum cobalt stack (Pt/Co)n, where n can be a positive integer. A transition layer 112 may be disposed between the first pinning layer 114 and the reference layer 106. The transition layer 112 is made of non-magnetic materials and is configured as a buffer layer, a lattice match layer, and/or a diffusion barrier. As an example, the transition layer 112 may comprise tantalum (Ta), tungsten (W), molybdenum (Mo), Hafnium (Hf), or CoFeW.

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