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Read circuit for magnetic tunnel junction (MTJ) memory

專利號
US10867652B2
公開日期
2020-12-15
申請人
Taiwan Semiconductor Manufacturing Co., Ltd.（TW Hsinchu）
發(fā)明人
Gaurav Gupta; Zhiqiang Wu
IPC分類
G11C11/00; G11C11/16; H01L27/22; H01L43/02; H01L43/10
技術(shù)領(lǐng)域
mtj,nlr,rnlr,memory,read,layer,imtj,current,cell,tmr
地域： Hsin-Chu

摘要

In some embodiments, the present application provides a memory device. The memory device includes a first current mirror transistor, a first pull-up read-enable transistor, an MTJ memory cell, a first pull-down read-enable transistor, and a first non-linear resistance device. The MTJ memory cell includes an MTJ memory element and a first access transistor. The first non-linear resistance device is coupled in series and between the first pull-up read-enable transistor and the first current mirror transistor. The first non-linear resistance device is configured to provide a first resistance when conducting a first current and a second resistance greater than the first resistance when conducting a second current smaller than the first current.

說明書

During a typical write operation to Row 1, a voltage VWL is applied to a word-line WL1, wherein the VWL is typically greater than or equal to a threshold voltage of the access transistors 104, thereby turning on the access transistors within Row 1 and coupling the bit-lines BL1-BLM to the MTJ memory elements 102 in the accessed cells (e.g., memory cells C1-1 through C1-M). Suitable voltages are applied to the bit-lines BL1-BLM and source-lines SL1-SLM, where the voltage on each bit-line is representative of a data value to be written to the memory cell attached to that bit-line. While Row1 is accessed, the word-lines of the other rows (WL2-WLN) remain off, such that the MTJ memory elements of the other cells remain isolated and are not written to or read from.

權(quán)利要求

1
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