FIG. 3 illustrates a block diagram for some embodiments of a reading circuit 300 that can be used in the memory device 200 of FIG. 2. For simplicity, an MTJ memory cell 100 is shown in FIG. 3, though it will be appreciated that additional memory cells can be arranged in parallel with the illustrated MTJ memory cell 100 via a bit line BL and a source line SL consistent with FIG. 2. The reading circuit 300 comprises a reading bias circuit 302. During a read operation, the reading bias circuit 302 provides a reading voltage Vread for the MTJ memory cell 100 and a reference cell 100′ and accordingly output an output signal. A current mirror circuit may be used as a load of the read bias circuit. A sense amplifier 304 may be used to generate a digital output signal by processing output signals of the reading bias circuit 302. For example, the reading bias circuit 302 may sense a read current IMTJ flowing through the MTJ cell 100 and a reference current IRef flowing through the reference cell and generate a sensing voltage V_mtj and a reference voltage V_ref to feed into the sense amplifier 304. A read enable circuit 308 can pull up a voltage level (e.g., a voltage level on the bit line BL) during the read operation, and a pull-down circuit 310 can pull down a voltage level (e.g., a voltage level on the source line SL) during the read operation.
