Read circuit for magnetic tunnel junction (MTJ) memory
地域：
Hsin-Chu
摘要
In some embodiments, the present application provides a memory device. The memory device includes a first current mirror transistor, a first pull-up read-enable transistor, an MTJ memory cell, a first pull-down read-enable transistor, and a first non-linear resistance device. The MTJ memory cell includes an MTJ memory element and a first access transistor. The first non-linear resistance device is coupled in series and between the first pull-up read-enable transistor and the first current mirror transistor. The first non-linear resistance device is configured to provide a first resistance when conducting a first current and a second resistance greater than the first resistance when conducting a second current smaller than the first current.
說明書
A first non-linear resistor (NLR) device 310 is coupled to the MJT cell 100 in series and provides a transmission path for the read current IMTJ. The first NLR device 310 may be connected between the read bias circuit 302, and the read enable circuit 306. The first NLR device 310 is configured to provide a resistance that provides adjustment for a current flowing through the MTJ cell 100. The resistance of the first NLR device 310 may decrease as the current conducting on the first NLR device 310 increases. In some embodiments, the first NLR device 310 is an S-type negative resistance (NR) such as a forwardly biased thyristor (e.g., silicon control rectifier (SCR), diac, triac, etc.).
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