The MTJ current path 402 includes a first current mirror transistor M3, a first pull-up read-enable transistor M7, the MTJ memory cell 100 (including an MTJ memory element MTJ and a first access transistor M1), and a first pull-down read-enable transistor M8. Bit-line (BL) and source-line (SL) are coupled to opposite ends of the MTJ memory cell 100. The BL is coupled to the MTJ memory element MTJ, and the SL is coupled to the first access transistor M1 and is separated from the MTJ memory element MTJ by the first access transistor M1. The reference current path 404 includes a second current mirror transistor M2; a second pull-up read-enable transistor M5; the reference MTJ memory cell 100′ (including a reference MTJ memory element Ref, which can be implemented as a resistor with a fixed resistance in some embodiments, and a second access transistor M9); and a second pull-down read-enable transistor M10. A reference bit-line (BL_Ref) and reference source-line (SL_Ref), which have lengths and resistances that are substantially equal to those of the BL and SL, are coupled to opposite ends of the reference MTJ memory cell 100′. The BL_Ref is coupled to the reference MTJ memory element Ref, and the SL_Ref is coupled to the second access transistor M9 and is separated from the reference MTJ memory element Ref by the second access transistor M9.