FIG. 3 illustrates a block diagram for some embodiments of a reading circuit that can be used in the memory device of FIG. 2.
FIG. 4A illustrates a circuit schematic for some embodiments of a data path that can be used in the memory device of FIG. 2.
FIG. 4B illustrates a circuit schematic for some alternative embodiments of a data path that can be used in the memory device of FIG. 2.
FIGS. 5-6 illustrate timing diagrams depicting some embodiments of reading operations for a memory device, such as the memory device shown in FIGS. 3-4B.
FIG. 7 illustrates a cross-sectional diagram showing some embodiments of a memory device that includes an MTJ memory element.
FIG. 8 illustrates a top view of the memory device of FIG. 7, as indicated by the cut-lines in FIG. 7.
FIG. 9 illustrates a flowchart of some embodiments of a method of reading the MTJ memory device.
FIG. 10 shows an example load line analysis of a series connection of an MTJ memory cell and a forward biased SCR used for reading the MTJ memory device.
DETAILED DESCRIPTION
