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Read circuit for magnetic tunnel junction (MTJ) memory

專利號
US10867652B2
公開日期
2020-12-15
申請人
Taiwan Semiconductor Manufacturing Co., Ltd.(TW Hsinchu)
發(fā)明人
Gaurav Gupta; Zhiqiang Wu
IPC分類
G11C11/00; G11C11/16; H01L27/22; H01L43/02; H01L43/10
技術領域
mtj,nlr,rnlr,memory,read,layer,imtj,current,cell,tmr
地域: Hsin-Chu

摘要

In some embodiments, the present application provides a memory device. The memory device includes a first current mirror transistor, a first pull-up read-enable transistor, an MTJ memory cell, a first pull-down read-enable transistor, and a first non-linear resistance device. The MTJ memory cell includes an MTJ memory element and a first access transistor. The first non-linear resistance device is coupled in series and between the first pull-up read-enable transistor and the first current mirror transistor. The first non-linear resistance device is configured to provide a first resistance when conducting a first current and a second resistance greater than the first resistance when conducting a second current smaller than the first current.

說明書

Using an MTJ with positive tunneling magnetoresistance (TMR) as an example for illustration. If the magnetization directions of the reference layer and free layer are in a parallel orientation, the MTJ is in a low-resistance state (P-state). If the magnetization directions of the reference layer and free layer are in an anti-parallel orientation, the MTJ is in a high-resistance state (AP-state). The insertion of the first NLR device 310 increases Ip, decrease Iap, and thereby increases a difference of Iap and Ip, and thus increase TMR. The first NLR device 310 provides a first resistance (rnlr) when the low-resistance state P-state is read and a second resistance (Rnlr) greater than the first resistance (rnlr) when the high-resistance state AP-state is read. Thus, the difference between Ip and Iap is increased. The effective TMR becomes: (RAP?RP)+(Rnlr?rnlr)}/(RPath+RP+RMOS+rSD). The insertion of the first NLR device 310 also provides more margin to design the reference memory cell 100′. The reference resistor Rref would be in a range between RAP+Rnlr and RP+rnlr, instead of in a smaller range between RAP and RP. The reference memory cell 100′ has a reference resistance greater than a sum of the first resistance (RP) of the MTJ memory cell 100 and the first resistance (rnlr) of the first NLR device 310 and smaller than a sum of the second resistance (RAP) of the MTJ memory cell 100 and the second resistance (Rnlr) of the first NLR device 310.

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