Referring now to FIG. 5, a description of some embodiments of how the data paths 400a, 400b can operate during read operations is provided with regards to a timing/waveform diagram. FIG. 5 shows waveforms for two read operations on a single MTJ memory cell superimposed over one another to show how the current and voltage levels relate to one another. FIG. 6 shows waveforms for two read operations of a reading operation without an NLR device for comparison purpose. For a first read operation, the MTJ is in a parallel state, such that the first read operation returns a low voltage (e.g., logical “0”). For the second read operation, the MTJ is in an anti-parallel state, such that the second read operation returns a high voltage (e.g., logical “1”). As shown in FIG. 5 and FIG. 6, when V(re) is active to enable read operation, V(scr_gate) is active, and V_mtj changes in response to I(Mtj). SA may generate V_out according to V01, which is changed in response to V_mtj. For a comparison circuit without NLR devices shown in FIG. 6, IP is 50.6 μA; IAP is 44.1 μA, and thus a sensed TMR is around 14.74%. A read time is about 7.4 ns. The SCR gate voltage is tuned to make sure that P-state current IP is same for comparison purpose. From simulated waveforms shown in FIG. 6, IP in the disclosed reading operation is 50.4 μA; IAP is 32.9 μA, and thus, the sensed TMR is around 53.19%. Also seen from the waveforms, a read time is about 5.4 ns. Thus, AP-state current IAP of the disclosed reading operation of FIG. 5 is reduced, and TMR for the proposed circuit is relatively high as compared to that of the reading operation of FIG. 6. Also, the disclosed circuit can perform read operations at higher read speed.
