The interconnect structure 704 is arranged over the substrate 706 and couples devices (e.g., transistors 710, 104) to one another. The interconnect structure 704 includes a plurality of IMD layers 726, 728, 730, and a plurality of metallization layers 732, 734, 736 which are layered over one another in alternating fashion. The IMD layers 726, 728, 730 may be made, for example, of a low κ dielectric, such as un-doped silicate glass, or an oxide, such as silicon dioxide. The metallization layers 732, 734, 736 include metal lines 738, 740, 742, which are formed within trenches, and which may be made of a metal, such as copper or aluminum. Contacts 744 extend from the bottom metallization layer 732 to the source/drain regions 724 and/or gate electrodes 714, 716; and vias 746 extend between the metallization layers 732, 734, 736. The contacts 744 and the vias 746 extend through dielectric-protection layers 750, 752 (which can be made of dielectric material and can act as etch stop layers during manufacturing). The dielectric-protection layers 750, 752 may be made of an extreme low-□ dielectric material, such as SiC, for example. The contacts 744 and the vias 746 may be made of a metal, such as copper or tungsten, for example.

MTJ memory elements 102a, 102b, which are configured to store respective data states, are arranged within the interconnect structure 704 between neighboring metal layers. The MTJ memory element 102a includes an MTJ, including a pinning layer 114, a metallic interlayer 116, a reference layer 106, a barrier layer 110, and a free layer 108.