FIG. 1 illustrates some embodiments of a magnetic tunnel junction (MTJ) memory cell 100 that can be used with various read techniques as provided herein. The MTJ memory cell 100 includes a magnetic tunnel junction (MTJ) memory element 102 and an access transistor 104. A bit-line (BL) is coupled to one end of the MTJ memory element 102, and a source-line (SL) is coupled to an opposite end of the MTJ memory element through the access transistor 104. Thus, application of a suitable word-line (WL) voltage to a gate electrode of the access transistor 104 couples the MTJ memory element 102 between the BL and the SL, and allows a bias to be applied over the MTJ memory element 102 through the BL and the SL. Consequently, by providing suitable bias conditions, the MTJ memory element 102 can be switched between two states of electrical resistance, a first state with a low resistance (the P-state, magnetization directions of the reference layer and the free layer are parallel) and a second state with a high resistance (the AP-state, magnetization directions of the reference layer and free layer are antiparallel), to store data.