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Apparatus and methods for controlling refresh operations

專利號
US10867660B2
公開日期
2020-12-15
申請人
MICRON TECHNOLOGY, INC.（US ID Boise）
發(fā)明人
Hiroshi Akamatsu
IPC分類
G11C7/00; G11C11/408; G11C5/04; G11C5/06; G11C29/18; G11C29/00; G11C8/12
技術領域
word,row,address,rwlj,radd2,redundant,refresh,circuit,signal,target
地域： ID ID Boise

摘要

An apparatus includes a first word line, a second word line and a control. The second word line is contiguous to the first word line. The control circuit includes a first defective address storing circuit and a first detection circuit. The first defective address storing circuit stores first enable information along with first defective address. The first enable information indicates whether or not the second word line is functional. The first detection circuit provides a first signal when the first word line is accessed. The first signal indicates whether or not the second word line is functional. The control circuit activates the second word line when the first signal indicates that the second word line is functional and does not activate the second word line when the first signal indicates that the second word line is not functional.

說明書

PRIORITY

This application is a continuation of U.S. patent application Ser. No. 16/112,471, filed Aug. 24, 2018, which is a continuation of U.S. patent application Ser. No. 15/888,993, filed Feb. 5, 2018, and issued as U.S. Pat. No. 10,153,031 on Dec. 11, 2018, which is a continuation of U.S. patent application Ser. No. 14/713,942, filed May 15, 2015, and issued as U.S. Pat. No. 9,922,694 on Mar. 20, 2018, which claims the benefit of priority from Japanese Patent Application No. 2014-105197 filed on May 21, 2014. The aforementioned applications and patent are incorporated herein by reference, in their entirety, for any purposes.

BACKGROUND

Since a DRAM (Dynamic Random Access Memory), which is a typical semiconductor memory device, stores information by the electric charge accumulated in a cell capacitor, the information is lost unless a refresh operation is periodically carried out. Therefore, Japanese Patent Application Laid-Open No. 2011-258259 discloses that a control device, which controls the DRAM, periodically issues a refresh command, which orders the refresh operation, to the DRAM. The refresh command is issued from the control device at a frequency that all word lines are certainly refreshed once in the period of one refresh cycle (for example, 64 msec).

However, depending on the history of access to memory cells, the information retention time of predetermined memory cells are reduced in some cases. Then, when the information retention time of the predetermined memory cells is reduced to less than the one refresh cycle, there has been a risk that part of the information may be lost even if the refresh command is issued at the frequency that all the word lines are refreshed once in the period of one refresh cycle.

權利要求

1
What is claimed is:1. A dynamic random access memory (plum), comprising:a memory cell array on a single semiconductor chip; the memory cell array including a plurality of normal memory cells coupled to a plurality of normal word lines, and a plurality of redundant memory cells coupled to a plurality of redundant word lines;a command decoder on the single semiconductor chip, the command decoder configured to activate a command signal responsive to a command input from an external controller; anda row control circuit on the single semiconductor chip, the row control circuit, when a number of access to a first normal row address corresponding to a defective one of the plurality of normal word lines exceeds a predetermined value, configured, responsive to the command signal, to:generate a second redundant row address based on a first redundant row address replaced from the first normal row address; andselect a first one of the plurality of redundant word lines corresponding to the second redundant row address.2. The DRAM of claim 1, wherein the first redundant row address corresponds to a third one of the plurality of redundant word lines, and the third one of the plurality of redundant word lines is adjacent to the first one of the plurality of redundant word lines.3. The DRAM of claim 2, wherein the command input from the external controller corresponds to an active command.4. The DRAM of claim 1, further comprising a mode register configured to receive a target-row refresh command to enter a target-row refresh mode, wherein the target-row refresh command is issued from the external controller when a number of access to the first normal row address exceeds the predetermined value.5. The DRAM of claim 4, wherein the row control circuit, in the target-row refresh mode, is configured to generate the second redundant row address based on the first redundant row address replaced from the first normal row address and select the first one of the plurality of redundant word lines corresponding to the second redundant row address.6. The DRAM of claim 5, wherein the command decoder, in the target-row refresh mode; is configured to activate the command signal responsive to an active command input from the external controller.7. The DRAM of claim 6, wherein the row control circuit, in the target-row refresh mode, is configured to generate the second redundant row address based on the first redundant row address replaced from the first normal row address and select the first one of the plurality of redundant word lines corresponding to the second redundant row address responsive to the active command signal.8. The DRAM of claim 1, wherein the row control circuit, after selecting the first one of the plurality of redundant word lines, is further configured, responsive to the command signal, to:generate a third redundant row address based on the first redundant row address; andselect a second one of the plurality of redundant word lines corresponding to the third redundant row address.9. The DRAM of claim 8, wherein the first redundant row address corresponds to a third one of the plurality of redundant word lines, and the third one of the plurality of word lines is adjacent to each of the first one and the second one of the plurality of redundant word lines.10. The DRAM of claim 9, wherein command input from the external controller corresponds to an active command.11. The DRAM of claim 9, further comprising a mode register configured to receive a target-row refresh command to enter a target-row refresh mode, wherein the target-row refresh command is issued from the external controller when a number of access to the first normal row address exceeds the predetermined value.12. The DRAM of claim 11, wherein the row control circuit, in the target-row refresh mode, is configured to:generate the second redundant row address based on the first redundant row address replaced from the first normal row address and select the first one of the plurality of redundant word lines corresponding to the second redundant row address; andgenerate the third redundant row address based on the first redundant row address and select the second one of the plurality of redundant word lines corresponding to the third redundant row address.13. The DRAM of claim 12, wherein the command decoder, in the target-row refresh mode, is configured to activate the command signal responsive to an active command input from the external controller and activate an additional command signal responsive to an additional active command input from the external controller.14. The DRAM of claim 13, wherein the row control circuit; in the target-row refresh mode; is configured to:generate the second redundant row address based on the first redundant row address replaced from the first normal row address and select the first one of the plurality of redundant word lines corresponding to the second redundant row address responsive to the active signal; andgenerate the third redundant row address based on the first redundant row address and select the second one of the plurality of redundant word lines corresponding to the third redundant row address responsive to the additional active signal.
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