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Apparatus and methods for controlling refresh operations

專利號
US10867660B2
公開日期
2020-12-15
申請人
MICRON TECHNOLOGY, INC.(US ID Boise)
發(fā)明人
Hiroshi Akamatsu
IPC分類
G11C7/00; G11C11/408; G11C5/04; G11C5/06; G11C29/18; G11C29/00; G11C8/12
技術領域
word,row,address,rwlj,radd2,redundant,refresh,circuit,signal,target
地域: ID ID Boise

摘要

An apparatus includes a first word line, a second word line and a control. The second word line is contiguous to the first word line. The control circuit includes a first defective address storing circuit and a first detection circuit. The first defective address storing circuit stores first enable information along with first defective address. The first enable information indicates whether or not the second word line is functional. The first detection circuit provides a first signal when the first word line is accessed. The first signal indicates whether or not the second word line is functional. The control circuit activates the second word line when the first signal indicates that the second word line is functional and does not activate the second word line when the first signal indicates that the second word line is not functional.

說明書

Although details will be described later, the row control circuit 28 includes many antifuse elements. The antifuse element is an element which is insulated in an initial state and, when subjected to dielectric breakdown by a connect operation, makes a transition to a conductive state. When the transition to the conductive state is once made by the connect operation, the antifuse element cannot be returned again to the insulated state. Therefore, the antifuse element can be used as a nonvolatile and irreversible storage element. The connect operation with respect to the antifuse element uses a high potential VPPSV and a negative potential VBBSV. The high potential VPPSV and the negative potential VBBSV is generated by a power-source circuit 30 based on a power-source potential VDD and a ground potential VSS.

In the mode register 27, a parameter indicating an operation mode of the semiconductor device 10 according to the present embodiment is set. For example, if the internal command/address signal iC/A is indicating a target-row refresh command, a parameter indicating a target-row refresh mode is registered in the mode register 27, and a target-row refresh enable signal TRREN is activated. The target-row refresh enable signal TRREN is supplied to the row control circuit 28.

FIG. 2 is a drawing for explaining address allocation of the normal word lines WL and the redundant word lines RWL.

權利要求

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