Furthermore, if access with respect to the redundant word line RWL0 shown in FIG. 2 is repeated, the information retention time of the normal memory cells MC connected to the normal word line WLN connected thereto and the redundant memory cells RMC connected to the redundant word line RWL1 are reduced. This case can be solved by executing the target-row refresh operation with respect to the normal word line WLN and the redundant word line RWL1. Also in this case (case 3), one of the word lines serving as the targets of the target-row refresh operation belongs to the normal-word-line area A1, and the other one belongs to the redundant-word-line area A2.

If access with respect to the redundant word line RWL2 shown in FIG. 2 is repeated, the information retention time of the redundant memory cells RMC connected to the redundant word lines RWL1 and RWL3 adjacent thereto are reduced. This case can be solved by executing the target-row refresh operation with respect to the redundant word lines RWL1 and RWL3. In this case (case 4), all of the word lines serving as the targets of the target-row refresh operation belong to the redundant-word-line area A2.

If the normal-word-line area A1 and the redundant-word-line area A2 are continuously provided to be mutually adjacent in this manner, the target-row refresh operations have to be executed in consideration of the above described four cases. Although this point will be described later in detail, in order to correctly execute the target-row refresh operations in any of the four cases, the present embodiment includes the circuits which are necessary for correctly carrying out the target-row refresh operations in a case of occurrence of any of the case 1 to the case 4.