As shown in FIG. 4, the state-signal generation circuit 34 includes a SR-type flip-flop circuit 51 and D-latch-type flip-flop circuits 52 to 54. The flip-flop circuit 51 is set by the target-row refresh enable signal TRREN and is reset by the output signal of the flip-flop circuit 54. The flip-flop circuit 51 provides a state signal TRRST1 to reset nodes of the flip-flop circuits 52 to 54. The reset nodes of the flip-flop circuits 52 to 54 employ negative logic. Therefore, if the target-row refresh enable signal TRREN is activated, the reset state of the flip-flop circuits 52 to 54 is cancelled.
The flip-flop circuits 52 to 54 are cascade-connected in this order, and all of them carry out latch operations in synchronization with the precharge signal iPRE. An input node of the flip-flop circuit 52 is fixed to a high level. The output signal of the flip-flop circuit 52 is used as the state signal TRRST2, and the output signal of the flip-flop circuit 53 is used as the state signal TRRST3. The output signal of the flip-flop circuit 54 resets the flip-flop circuit 51 as described above.
FIG. 5 is a timing diagram for explaining the operations of the state-signal generation circuit 34.
