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Apparatus and methods for controlling refresh operations

專利號
US10867660B2
公開日期
2020-12-15
申請人
MICRON TECHNOLOGY, INC.(US ID Boise)
發(fā)明人
Hiroshi Akamatsu
IPC分類
G11C7/00; G11C11/408; G11C5/04; G11C5/06; G11C29/18; G11C29/00; G11C8/12
技術(shù)領(lǐng)域
word,row,address,rwlj,radd2,redundant,refresh,circuit,signal,target
地域: ID ID Boise

摘要

An apparatus includes a first word line, a second word line and a control. The second word line is contiguous to the first word line. The control circuit includes a first defective address storing circuit and a first detection circuit. The first defective address storing circuit stores first enable information along with first defective address. The first enable information indicates whether or not the second word line is functional. The first detection circuit provides a first signal when the first word line is accessed. The first signal indicates whether or not the second word line is functional. The control circuit activates the second word line when the first signal indicates that the second word line is functional and does not activate the second word line when the first signal indicates that the second word line is not functional.

說明書

In order to solve such a problem, recently, a technique which restores the electric charge with respect to the information-retention-time-reduced memory cells by utilizing the history of access to the memory cells has been studied. This technique is called target-row refresh.

Herein, in a case in which a defective word line is replaced by a redundant word line, erroneous operations may occur unless the target-row refresh operation is carried out in consideration of that. This is for a reason that actually-used (functional) redundant word lines and unused (non-functional) redundant word lines are mixed in the redundant word lines. More specifically, when the unused redundant word line is selected in a target-row refresh operation, for example, if micro short-circuit is present at the unused redundant word line or the memory cells connected thereto, there has been a risk that other data may be broken.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram showing a configuration of a semiconductor device according to an embodiment of the present invention.

FIG. 2 is a drawing showing address allocation of normal word lines and redundant word lines according to an embodiment of the present invention.

FIG. 3 is a block diagram showing a configuration of a row control circuit according to an embodiment of the present invention.

FIG. 4 is a circuit diagram of a state-signal generation circuit according to an embodiment of the present invention.

權(quán)利要求

1
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