Furthermore, OR gate circuits 66 are inserted to an output node of the selector 64. In FIG. 6, the OR gate circuit 66 is shown by one symbol mark. However, in practice, the OR gate circuits 66 are inserted respectively for the bits Xn to X0 of the row address RADD1a. The flag signal FLG2 is input to the OR gate circuits 66. Therefore, if the flag signal FLG2 is activated to the high level, the values of the row address RADD1a are forced to be maximum values, in other words, all of the values Xn to X0 become “I”. The word line at which all of the values Xn to X0 are “I” corresponds to the normal word line WLN shown in FIG. 2.
The selection signals SEL2 and SEL3 are generated by a logic circuit 60 shown in FIG. 7. The operations of the logic circuit 60 are shown in FIG. 5. The selection signal SEL2 is activated to the high level in the period from the first precharge signal iPRE to the second precharge signal iPRE, and the selection signal SEL3 is activated to the high level in the period from the second precharge signal iPRE to the third precharge signal iPRE.
