If none of the hit signals HIT0 to HITm is activated, the selector 39 selects the row address RADD2 and supplies this to a row predecoder 41. On the other hand, if any of the hit signals HIT0 to HITm is activated, the selector 39 selects the row address RADD3 and supplies this to the row predecoder 41.

The row predecoder 41 controls a row decoder 42 by predecoding the row address RADD2 or RADD3. The row decoder 42 includes a normal-word-line row decoder and a redundant-word-line row decoder and selects the normal word line WL or the redundant word line RWL by completely decoding the row address RADD2 or RADD3. Specifically, if the selector 39 is selecting the row address RADD2, any of the normal word line WL is selected by the row decoder 42. On the other hand, if the selector 39 is selecting the row address RADD3, any of the redundant word line RWL is selected by the row decoder 42. The row predecoder 41 and the row decoder 42 constitute a word-line drive circuit.

FIG. 10 is a circuit diagram of the fuse set FSETk.

As shown in FIG. 10, the fuse set FSETk includes antifuse circuits AFC1 to AFCn (first storage unit) and an enable circuit ENC (second storage unit). The antifuse circuits AFC1 to AFCn are the circuits respectively corresponding to the bits X1 to Xn of the address RADD2, and each of them includes the antifuse element AF, a load circuit 71, and a comparison circuit 72. The antifuse circuit corresponding to the least significant bit X0 of the address RADD2 is not provided.