As shown in FIG. 15, the address conversion circuit 43 includes an AND gate circuit 93, which receives the flag signal FLG1, the usage detection signal USE0, and the state signal TRRST3; and a switch circuit 94, which is activated by the output signal of the AND gate circuit 93. If the output signal of the AND gate circuit 93 becomes the high level, the switch circuit 94 activates a switch signal FRC0. If the switch signal FRC0 is activated, regardless of the values of the row addresses RADD2 and RADD3 input from the selector 39, the redundant word line RWL0 is forcibly selected by the row decoder 42. Therefore, if both of the flag signal FLG1 and the usage detection signal USE0 are activated, the redundant word line RWL0 is forcibly selected in response to the state signal TRRST3.
FIG. 16 is a circuit diagram of the address conversion circuit 44 contained in the row predecoder 41.
