As shown in FIG. 16, the address conversion circuit 44 includes an AND gate circuit 95, which receives the inverted signal of the flag signal FLG1, the flag signal FLG3, and the state signal TRRST3; and a switch circuit 96, which is activated by the output signal of the AND gate circuit 95. If the output signal of the AND gate circuit 95 becomes the high level, the switch circuit 96 activates a switch signal FRC1. If the switch signal FRC1 is activated, the value of the row address RADD3 input from the selector 39 is changed, and among the redundant word lines RWL adjacent to the redundant word line RWL corresponding to the row address RADD3, the redundant word line RWL in the opposite side of the redundant word line RWL at which only the least significant bit RX0 of the replacement addresses Rxn to RX0 is different is forcibly selected. Therefore, if the flag signal FLG1 is deactivated and the flag signal FLG3 is activated, the redundant word line RWL adjacent to the redundant word line RWL corresponding to the row address RADD3 is selected in response to the state signal TRRST3.
The circuit configuration of the semiconductor device 10 according to the present embodiment is as described above. Next, the operations of the semiconductor device 10 according to the present embodiment will be explained for each case with reference to FIG. 17 to FIG. 22.
[Case 1]
