In this state, a first target-row refresh operation is carried out in a below manner. First, the target address, in other words, the row address of the normal word line WLi, in other words, the target address (described as “Target Row” in FIG. 17) is input together from an active command ACT from the controller (time t12). As a result, the command decoder 25 activates the active signal iACT. Therefore, the row control circuit 28 executes row access.
Since the state signals TRRST2 and TRRST3 are at the low level at this point of time, the selector 31 shown in FIG. 3 selects the row address RADD1 (target address) input from outside, and this is output as the row address RADD2. The row address RADD2 is input to the address detection circuit 35. However, in the present case, the target address is not a defective address, and none of the hit signals HIT0 to HITm are therefore activated. Moreover, since the normal word line WL indicated by the target address is not the normal word line WLN adjacent to the redundant-word-line area A2 in the present case, the flag signal FLG1 is also at the low level. Furthermore, since none of the hit signals HIT0 to HITm are activated, the flag signals FLG2 and FLG3 are also at the low level.
