Therefore, the row predecoder 41 and the row decoder 42 select the normal word line WLi indicated by the target address input from outside, and the normal memory cells MC connected thereto are refreshed. Then, when a precharge command PRE is issued, the precharge signal iPRE is generated by the command decoder 25, and the state signal TRRST2 is changed to the high level (time t13). As a result, the selection signal SEL2 also becomes the high level.

The first target-row refresh operation is completed as described above. In this manner, in the first target-row refresh operation, the normal word line WLi indicated by the target address is selected. FIG. 17 shows the case in which the target address corresponds to the normal word line WL2.

Then, a second target-row refresh operation is carried out. First, the target address is input again together with an active command ACT from the controller (time t14). As a result, the row control circuit 28 executes row access again. However, since the state signal TRRST2 is at the high level at this point of time, the selector 31 selects the row address RADD1a output from the address control circuit 32 and outputs that as the row address RADD2. Since the selection signal SEL2 is activated to the high level, the address control circuit 32 inverts the least significant bit X0 of the input target address and outputs this as the row address RADD1a.