Apparatus and methods for controlling refresh operations
摘要
說(shuō)明書(shū)
The more significant bits Xn to X1 of the row address RADD2 generated in this manner excluding the least significant bit X0 are the same as the more significant bits Xn to X1 of the target address. Therefore, as a matter of course, none of the hit signals HIT0 to HITm are activated.
Therefore, the row predecoder 41 and the row decoder 42 select the normal word line WLi?1 or WLi+1 (for example, the normal word line WL3) adjacent to one side of the normal word line WLi indicated by the target address input from outside, and the normal memory cells MC connected thereto are refreshed. Then, when a precharge command PRE is issued, the state signal TRRST3 is changed to the high level (time t15). As a result, the selection signal SEL3 becomes the high level instead of the selection signal SEL2.
The second target-row refresh operation is completed as described above. In this manner, in the second target-row refresh operation, the normal word line WLi?1 or WLi+1 adjacent to the one side of the normal word line WLi indicated by the target address is selected. The normal word line WLi and the normal word line WLi?1 or WLi+1 are the word lines at which only the least significant bits X0 are different.
