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Apparatus and methods for controlling refresh operations

專利號
US10867660B2
公開日期
2020-12-15
申請人
MICRON TECHNOLOGY, INC.（US ID Boise）
發(fā)明人
Hiroshi Akamatsu
IPC分類
G11C7/00; G11C11/408; G11C5/04; G11C5/06; G11C29/18; G11C29/00; G11C8/12
技術(shù)領(lǐng)域
word,row,address,rwlj,radd2,redundant,refresh,circuit,signal,target
地域： ID ID Boise

摘要

An apparatus includes a first word line, a second word line and a control. The second word line is contiguous to the first word line. The control circuit includes a first defective address storing circuit and a first detection circuit. The first defective address storing circuit stores first enable information along with first defective address. The first enable information indicates whether or not the second word line is functional. The first detection circuit provides a first signal when the first word line is accessed. The first signal indicates whether or not the second word line is functional. The control circuit activates the second word line when the first signal indicates that the second word line is functional and does not activate the second word line when the first signal indicates that the second word line is not functional.

說明書

FIG. 15 is a circuit diagram of an address conversion circuit contained in a row predecoder according to an embodiment of the present invention.

FIG. 16 is a circuit diagram of an address conversion circuit contained in the row predecoder according to an embodiment of the present invention.

FIG. 17 is a timing chart showing target-row refresh operations in a case 1.

FIG. 18 is a first timing chart showing target-row refresh operations in a case 2.

FIG. 19 is a second timing chart showing target-row refresh operations in a case 2.

FIG. 20 is a timing chart showing target-row refresh operations in a case 3.

FIG. 21 is a first timing chart showing target-row refresh operations in a case 4.

FIG. 22 is a timing chart showing target-row refresh operations in the case 2.

DETAILED DESCRIPTION

權(quán)利要求

1
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