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Apparatus and methods for controlling refresh operations

專利號
US10867660B2
公開日期
2020-12-15
申請人
MICRON TECHNOLOGY, INC.(US ID Boise)
發(fā)明人
Hiroshi Akamatsu
IPC分類
G11C7/00; G11C11/408; G11C5/04; G11C5/06; G11C29/18; G11C29/00; G11C8/12
技術(shù)領(lǐng)域
word,row,address,rwlj,radd2,redundant,refresh,circuit,signal,target
地域: ID ID Boise

摘要

An apparatus includes a first word line, a second word line and a control. The second word line is contiguous to the first word line. The control circuit includes a first defective address storing circuit and a first detection circuit. The first defective address storing circuit stores first enable information along with first defective address. The first enable information indicates whether or not the second word line is functional. The first detection circuit provides a first signal when the first word line is accessed. The first signal indicates whether or not the second word line is functional. The control circuit activates the second word line when the first signal indicates that the second word line is functional and does not activate the second word line when the first signal indicates that the second word line is not functional.

說明書

FIG. 18 is a first timing chart for explaining the target-row refresh operations in the case 2. The case 2 is that access with respect to the normal word line WLN adjacent to the redundant-word-line area A2 has been repeated, the target-row refresh operations are executed with respect to the normal word line WLN?1 and the redundant word line RWL0 adjacent thereto. More specifically, this is the case in which the word line serving as the cause of the target-row refresh operations belongs to the normal-word-line area A1, one of the word lines serving as the target of the target-row refresh operation belongs to the normal-word-line area A1, and the other one belongs to the redundant-word-line area A2. In this case, it is assumed that the normal word line WLN is not defective. Herein, in the case 2, a case in which the redundant word line RWL0 is used is explained.

First, when the number of access with respect to the normal word line WLN exceeds a predetermined value, a target-row refresh command TRR is issued from the external controller (time t21). As a result, the target-row refresh enable signal TRREN output from the mode register 27 is activated. Therefore, the state signal TRRST1 becomes the high level.

In this state, a first target-row refresh operation is carried out in the below manner. First, the target address, in other words, the row address of the normal word line WLN is input together with an active command from the controller (time t22). The operation related thereto is as explained by using FIG. 17, wherein the normal word line WLN indicated by the target address input from outside is selected, and the normal memory cells MC connected thereto are refreshed.

權(quán)利要求

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