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Apparatus and methods for controlling refresh operations

專利號(hào)
US10867660B2
公開日期
2020-12-15
申請(qǐng)人
MICRON TECHNOLOGY, INC.（US ID Boise）
發(fā)明人
Hiroshi Akamatsu
IPC分類
G11C7/00; G11C11/408; G11C5/04; G11C5/06; G11C29/18; G11C29/00; G11C8/12
技術(shù)領(lǐng)域
word,row,address,rwlj,radd2,redundant,refresh,circuit,signal,target
地域： ID ID Boise

摘要

An apparatus includes a first word line, a second word line and a control. The second word line is contiguous to the first word line. The control circuit includes a first defective address storing circuit and a first detection circuit. The first defective address storing circuit stores first enable information along with first defective address. The first enable information indicates whether or not the second word line is functional. The first detection circuit provides a first signal when the first word line is accessed. The first signal indicates whether or not the second word line is functional. The control circuit activates the second word line when the first signal indicates that the second word line is functional and does not activate the second word line when the first signal indicates that the second word line is not functional.

說明書

However, in the case 2, all of the values indicating the normal word line WLN by the target address, in other words, the values of Xn to X0 are “1”. Therefore, the AND gate circuit 78 contained in the boundary detection circuit 36 is outputting the high level.

Then, when a precharge command PRE is issued, the state signal TRRST2 and the selection signal SEL2 are changed to the high level (time t23). As a result, the latch circuit 79 contained in the boundary detection circuit 36 latches the signal at the high level. Therefore, the flag signal FL

G is activated to the high level.

The first target-row refresh operation is completed as described above. In this manner, in the first target-row refresh operation, the normal word line WLN indicated by the target address is selected.

Then, a second target-row refresh operation is carried out. First, the target address is input again together with an active command ACT from the controller (time t24). The operation related thereto is as explained by using FIG. 17, wherein the row address RADD2 having the inverted least significant bit X0 of the target address input from outside is generated, and the normal word line WLN?1 corresponding thereto is selected.

Then, when a precharge command PRE is issued, the state signal TRRST3 and the selection signal SEL3 are changed to the high level (time t25).

權(quán)利要求

1
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