Then, the target address is input in relation to a third target-row refresh operation (time t46). However, since the flag signal FLG2 is at the high level in the present example, all of the values of Xn to X0 of the row address RADD1a output from the address control circuit 32 become “I”. The word line at which all of the values of Xn to X0 are “1” corresponds to the normal word line WLN shown in FIG. 2. As a result, in the third target-row refresh operation, regardless of the input target address, the normal word line WLN is selected. Note that the output signal of the AND gate circuit 78 contained in the boundary detection circuit 36 is at the high level. However, since the state signal TRRST2 is already at the high level at this point of time, the latch circuit 79 does not carry out a latch operation. Therefore, the flag signal FLG1 is maintained at the low level.

In this manner, in the case 3, the redundant word line RWL0, which is the replacement destination, the redundant word line RWL1 adjacent to the one side of the redundant word line RWL0, and the normal word line WLN adjacent to the other side of the redundant word line RWL0 are sequentially selected.

Note that, the above described example has been explained on the assumption that the normal word line WLN is not defective. However, if the normal word line WLN is defective and replaced by the redundant word line RWL, the redundant word line RWL, which is the replacement destination, is selected in the third target-row refresh operation. However, this operation is not essential.

[Case 4 (Number 1)]