Certain details are set forth below to provide a sufficient understanding of embodiments of the invention. However, it will be clear to one skilled in the art that embodiments of the invention may be practiced without these particular details. Moreover, the particular embodiments of the present invention described herein are provided by way of example and should not be used to limit the scope of the invention to these particular embodiments. In other instances, well known circuits, control signals, timing protocols, and software operations have not been shown in detail in order to avoid unnecessarily obscuring the invention.

FIG. 1 is a block diagram showing a configuration of a semiconductor device 10 according to the embodiment of the present invention.

The semiconductor device 10 according to the present embodiment is, for example, a DDR4 (Double Data Rate 4) type DRAM integrated on a single semiconductor chip and carries out read operations and write operations with respect to a memory cell array 20 based on external clock signals CLK and command/address signals C/A, which are input from an external controller. Data signals DATA which are read from the memory cell array 20 in the read operations are output to outside via a data control circuit 21 and a data input/output circuit 22. Data signals DATA which are input from outside in the write operations are written to the memory cell array 20 via the data input/output circuit 22 and the data control circuit 21.