The operations corresponding to time t61 to t65 are similar to those of FIG. 21. More specifically, the redundant word line RWLj is selected in a first target-row refresh operation, and the redundant word line RWLj?1 or RWLj+1 is selected in a second target-row refresh operation. Then, the target address is input in relation to a third target-row refresh operation (time t66). In the present example, the redundant word line RWLj?1 or RWLj+1 is unused; therefore, it is assumed that the enable signal AFENk?1 is at the low level if the least significant bit X0 of the row address is “0”, and the enable signal AFENk+1 is at the low level if the least significant bit X0 of the row address is “1”. Therefore, the usage detection signal USEk maintains the low level. Therefore, even if the state signal TRRST2 is activated, the flag signal FLG3 is maintained at the low level. Therefore, forcible address conversion by the address conversion circuit 44 is not carried out, and, also in the third target-row refresh operation, the redundant word line RWLj?1 or RWLj+1 is selected again as well as the second one.

If the redundant word line RWLj?1 or RWLj+1 is unused in the case 4 in this manner, the redundant word line RWLj, which is the replacement destination, and the redundant word line RWLj?1 or RWLj+1 adjacent to the one side of the redundant word line RWLj are sequentially selected, while the redundant word line RWLj?1 or RWLj+1 adjacent to the other side is not selected. As a result, unexpected erroneous operations caused by selecting the unused redundant word line RWL are prevented.