The read/write signal iW/R is activated when the internal command/address signal iC/A is indicating a read command or a write command. When the internal command/address signal iC/A is indicating the read command or the write command, the column control signal CCTL is also activated. When the read/write signal iW/R is activated, a column address contained in the internal command/address signal iC/A is latched by the address latch circuit 26. The column address CADD latched by the address/latch circuit 26 is supplied to a column control circuit 29. When the column control signal CCTL is activated, the column control circuit 29 selectively connects any of a plurality of bit lines BL, which are contained in the memory cell array 20, to a corresponding sense amplifier SA based on the column address CADD. FIG. 1 shows a single bit line BL in the memory cell array 20. However, in practice, many bit lines BL are provided. The bit lines BL are connected to sense amplifiers SA, and read or write of the data signals DATA is carried out via the sense amplifiers SA.

More specifically, in a read operation, the data signal DATA is read from a normal memory cell MC disposed at the intersection point of the selected normal word line WL and the selected bit line BL or a redundant memory cell RMC disposed at the intersection point of the selected redundant word line RWL and the selected bit line BL, and the data signal DATA is output to outside via the data control circuit 21 and the data input/output circuit 22.