On the other hand, in a write operation, the data signal DATA input from outside is supplied to the memory cell array 20 via the data input/output circuit 22 and the data control circuit 21, and the data signal DATA is written to a normal memory cell MC disposed at the intersection point of the selected normal word line WL and the selected bit line BL or a redundant memory cell RMC disposed at the intersection point of the selected redundant word line RWL and the selected bit line BL.

The refresh signal iREF is activated when the internal command/address signal iC/A is indicating a refresh command. The refresh signal iREF is supplied to the row control circuit 28, thereby executing a refresh operation of normal memory cells MC or redundant memory cells RMC.

The precharge signal iPRE is activated when the internal command/address signal iC/A is indicating a precharge command. The precharge signal iPRE is supplied to the row control circuit 28, thereby deactivating the normal word line WL or the redundant word line RQL which have been activated.

The address selection signal ADDSEL is activated when the internal command/address signal iC/A is indicating the active command or the refresh command. The address selection signal ADDSEL is supplied to the row control circuit 28, thereby executing selection of the normal word line WL or the redundant word line RWL serving as an access target.