Main word line driver circuit
地域：
ID
ID Boise
摘要
A main word line circuit provides a first and second row factor signals. The main word line circuit includes a pull-up circuit to drive a global word line to follow a first decoded address signal when the first row factor signal is at a first value. The main word line circuit includes an intermediate voltage circuit to drive the global word line to follow a value of the second row factor signal. A processing device drives the global word line to an active state by setting the first row factor signal to the first value when the first decoded address signal is at a high state, and drives the global word line to follow a value of the second row factor signal by setting the first row factor signal to the second value while the first decoded address signal is at the high state.
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This application contains subject matter related to an U.S. Patent Application by Charles L. Ingalls et al., titled “FX DRIVER CIRCUIT”. The related application is assigned to Micron Technology, Inc., and is identified as U.S. patent application Ser. No. 16/399,159, filed Apr. 30, 2019. The subject matter thereof is incorporated herein by reference thereto.
This application contains subject matter related to an U.S. Patent Application by Charles L. Ingalls et al., titled “SUB-WORD LINE DRIVER CIRCUIT”. The related application is assigned to Micron Technology, Inc., and is identified as U.S. patent application Ser. No. 16/399,197, filed Apr. 30, 2019. The subject matter thereof is incorporated herein by reference thereto.
This application contains subject matter related to an U.S. Patent Application by Christopher J. Kawamura et al., titled “DRAM ARRAY ARCHITECTURE WITH ROW HAMMER STRESS MITIGATION”. The related application is assigned to Micron Technology, Inc., and is identified as U.S. patent application Ser. No. 16/399,283, filed Apr. 30, 2019. The subject matter thereof is incorporated herein by reference thereto.
Embodiments of this invention relate to signal drivers for word line circuits and methods of driving a word line in a memory device.
權(quán)利要求
We claim:1. A main word line circuit for a memory device, comprising:a RF driver circuit configured to provide a first row factor signal and a second row factor signal; a main word line driver circuit including,a pull-up circuit configured to receive the first row factor signal and a first decoded address signal, the pull-up circuit further configured to drive a global word line to follow the first decoded address signal when the first row factor signal is at a first value and isolate the first decoded address signal from the global word line signal when the first row factor signal is at a second value, and an intermediate voltage circuit configured to receive the first decoded address signal and the first and second row factor signals, the intermediate circuit further configured to drive the global word line to follow a value of the second row factor signal; and a processing device operatively coupled to the RF driver circuit, the processing device configured to,drive the global word line to an active state by setting the first row factor signal to the first value when the first decoded address signal is at a high state, and drive the global word line to follow a value of the second row factor signal by setting the first row factor signal to the second value while the first decoded address signal is at the high state, wherein the value of the second row factor signal is at an intermediate voltage level that is below a voltage level of the active state and above a voltage level of a pre-charge state. 2. The main word line circuit of claim 1 , further comprising:a pull-down circuit configured to receive the second decoded address signal and a low voltage signal, the pull-down circuit further configured to drive the global word line to a value of the low voltage signal if the second decoded address signal is at a third value, wherein the processing device is further configured to drive the global word line to the pre-charge state by setting the second decoded address signal to the third value and setting the first row factor signal at the second value. 3. The main word line circuit of claim 1 , wherein the RF driver circuit receives a timing signal, andwherein the RF driver circuit is configured such that the first row factor signal is set to the first value based on a first state of the timing signal and is set to the second value based on a second state of the timing signal, the second state being opposite the first state. 4. The main word line circuit of claim 2 , wherein the RF driver circuit receives a first timing signal and a second timing signal,wherein the RF driver circuit is configured such that the second row factor signal has the intermediate voltage level when the first timing signal is at a first state and the second timing signals is at a second state that is opposite the first state. 5. The main word line circuit of claim 1 , wherein the intermediate voltage level is in a range of 0.25 volts to 0.75 volts. 6. The main word line circuit of claim 1 , wherein the intermediate voltage level is 0.5 volts. 7. The main word line circuit of claim 2 , wherein the pull-up circuit includes a PMOS transistor with a gate connected to the first row factor signal, a source connected to the first decoded address signal, and a drain connected to the global word line,wherein the intermediate voltage circuit includes a first NMOS transistor with a source connected in series to a drain of a second NMOS transistor, the gate of the first NMOS transistor connected to the first decoded address signal and the gate of the second NMOS transistor connected to the first row factor signal, the source of the second NMOS transistor connected to the second row factor signal and the drain of the first NMOS transistor connected to the global word line, and wherein the pull-down transistor includes a third NMOS transistor with a gate connected to the second decoded address signal, a source connected to the low voltage signal, and a drain connected to the global word line. 8. A method, comprising:generating a first row factor signal and a second row factor signal in a memory device; driving a global word line of the memory device to an active state by setting the first row factor signal to a first value when a first decoded address signal is at a high state, and driving the global word line to follow a value of the second row factor signal by setting the first row factor signal to a second value while the first decoded address signal is at the high state, wherein the value of the second row factor signal is at an intermediate voltage level that is below a voltage level of the active state and above a voltage level of a pre-charge state. 9. The method of claim 8 , further comprising:driving the global word line to the pre-charge state by setting the second decoded address signal to the third value to drive the global word line to a value of a low voltage source and by setting the first row factor at the second value. 10. The method of claim 8 , further comprising:setting the first row factor signal to the first value based on a first state of a timing signal of a driver circuit of the memory device; and setting the first row factor signal to the second value based on a second state of the timing signal, the second state being opposite the first state. 11. The method of claim 9 , further comprising:setting the second row factor signal to the intermediate voltage level when a first timing signal of a driver circuit in the memory device is at a first state and a second timing signals of the driver circuit is at a second state that is opposite the first state. 12. The method of claim 8 , wherein the intermediate voltage level is in a range of 0.25 volts to 0.75 volts. 13. The method of claim 12 , wherein the intermediate voltage level is 0.5 volts. 14. The method of claim 8 , wherein the voltage level of the pre-charge state is ?0.2 volts. 15. A non-transitory computer-readable storage medium comprising instructions that, when executed by a processing device, cause the processing device to:generate a first row factor signal and a second row factor signal in a memory device; drive a global word line of the memory device to an active state by setting the first row factor signal to a first value when a first decoded address signal is at a high state, and drive the global word line to follow a value of the second row factor signal by setting the first row factor signal to a second value while the first decoded address signal is at the high state, wherein the value of the second row factor signal is at an intermediate voltage level that is below a voltage level of the active state and above a voltage level of a pre-charge state. 16. The non-transitory computer-readable storage medium of claim 15 , further causing the processing device to:drive the global word line to the pre-charge state by setting the second decoded address signal to the third value to drive the global word line to a value of a low voltage source and by setting the first row factor at the second value. 17. The non-transitory computer-readable storage medium of claim 15 , further causing the processing device to:set the first row factor signal to the first value based on a first state of a timing signal of a driver circuit of the memory device; and set the first row factor signal to the second value based on a second state of the timing signal, the second state being opposite the first state. 18. The non-transitory computer-readable storage medium of claim 16 , further causing the processing device to:set the second row factor signal to the intermediate voltage level when a first timing signal of a driver circuit in the memory device is at a first state and a second timing signals of the driver circuit is at a second state that is opposite the first state. 19. The non-transitory computer-readable storage medium of claim 15 , wherein the intermediate voltage level is in a range of 0.25 volts to 0.75 volts. 20. The non-transitory computer-readable storage medium of claim 19 , wherein the intermediate voltage level is 0.5 volts.
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